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COURSES - ADVANCED RANDOM DEVELOPMENT


Length: Three days

Course objectives:

After attending this course the participant should be able to develop simulation environments with the key considerations which make them viable for coverage driven testing. In addition the participant will gain knowledge about the different tool kits available for his work.

Course description:

The course presents a series of design patterns and advanced technologies for architecting and writing advanced test benches.

The principles and design patterns learned are exercised in a series of exercises designed to accent the learning process while trying out solutions on real code and real simulations

Section Headers:

Designing for Random

There are a number of key areas which should be addressed during the design of verification modules to ensure they can be used well during coverage driven verification. This section will teach the definition of modules for random, by use of examples in the 'e' language

Skeleton of an Environment

A number of conventions have been developed to allow for simulation environments to be standard, portable and user friendly. This section describes an example of a skeletal outline of an HVL environment and how it is used to maximize sharing between block/cluster/full-chip level simulation.

Generation in e

This section provides a brief primer on use of Generation in the 'e' programming language.

Drivette Theory

One of the newly emerging design patterns employed for constrained random configuration of a design is called a 'drivette'. This section describes the design and use of drivettes to successfully build a highly random configuration for a design.

Transformations

As data-flow is processed in an RTL design various decisions are made on the resulting data flow (content, exit port, order etc.). This section describes a design pattern which can be employed to process data going into the design and build an expected scoreboard for the data in a simple and intuitive manner.

Registers

This section provides a design pattern for definition of registers. Using this design pattern, drivettes, coverage, and generation can all benefit from details of each register as they are defined in the specification document.

Designing Checkers

Checkers are an essential element in validating that given a scenario, the design performed according to expectation. In this section several types of checkers are described along with examples of coding these checkers.

Target Audience: Engineers experienced in writing 'e' wanting to advance their knowledge in architecting and designing advanced environments for coverage driven testing.

 

 

Design right. Verify right. Ace Verification

 


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