SystemVerilog is hardware description and verification language (HDVL) standard – it is an extension of the Verilog language, and was developed by Accellera to improve productivity in the design of large chips. SystemVerilog is targeted at both the chip implementation and verification flow.

SystemVerilog incorporates an assertion language and many of the verification constructs of Vera (HVL) into the Verilog language. By placing components common to HVLs (High level data structures, Functional Coverage, and Random capabilities) into the Verilog language, the potential for highly integrated tools is increased significantly.

One of the unique things about SystemVerilog is that it has become the accepted standard by Mentor Graphics, Cadence and Synopsys. As each of the major simulator vendors supports the language, it will be fair to assume that the SystemVerilog will become the predominate design language for new designs in the years to come.

The most effective use of SystemVerilog will be by teams who use the Coverage Revealed training on SystemVerilog.

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